FIG. 21 shows a structure of a conventional source driver provided in a driver of a display apparatus. As shown in the figure, the source driver 902 includes a shift register 904, a pulse processing circuit 905, and a buffer 920. The shift register 904 includes a large number of shift register stages (circuits) SR. Among them, an (i−1)-th shift register circuit SRa, an i-th shift register circuit SRb, (i+1)-th shift register circuit SRc, and an (i+2)-th shift register circuit SRd are discussed here. Each shift register circuit SR includes a flip-flop SR-FF and a level shifter LS. The level shifter LS serves to carry out level shift of clocks (SCK and SCKB), which are fetched when the EN terminal is active, and outputs the results through an OUTB. The flip-flop SR-FF is a set-reset type flip-flop having an input SB (set bar), a reset R, and outputs Q and QB. For example, the shift register circuit SRa includes a level shifter LSa and a flip-flop SR-FFa, a shift register circuit SRb includes a level shifter LSb and a flip-flop SR-FFb, a shift register circuit SRc includes a level shifter LSc and a flip-flop SR-FFc, and a shift register circuit SRd includes a level shifter LSd and a flip-flop SR-FFd.
An i-th shift register circuit SR is connected to the OUTB of a level shifter LS in the same stage via its SB, and connected to the Q of the (i+2)-th shift register circuit SR (the second adjacent shift register circuit to the right of the figure) via its R, and also connected to an EN terminal of a level shifter LS provided in a (i+1)-th shift register circuit SR (the adjacent shift register circuit to the right of the figure) via its Q.
Further, the pulse processing circuit 905 includes a delay circuit corresponding to each shift register circuit SR. The buffer 920 includes a pre-charge buffer circuit BuP and a sampling buffer circuit BuS corresponding to each shift register circuit SR.
The pre-charge buffer circuit BuP outputs a pre-charge pulse, and the sampling buffer circuit BuS outputs a sampling pulse. For example, corresponding to the i-th shift register circuit SRb, the pulse processing circuit 905 includes a delay circuit 906 and a delay circuit 910, the pre-charge buffer circuit BuS includes an inverter circuit 918P which is a cascade two-stage circuit and an inverter 919P, and the sampling buffer BuS includes an inverter circuit 918S which is a cascade two-stage circuit and an inverter 919S. Note that, each of the delay circuits 906 and 910 is a cascade four-stage circuit. Note that, the inverter circuit 918P, the inverter circuit 918S, and the delay circuits 906 and 910 each have a single input terminal and a single output terminal.
The input of the delay circuit 906 is connected to the OUTB of the level shifter LSa (provided in the (i−1)-th shift register circuit SRa), and the output of the delay circuit 906 is connected to the input of the inverter circuit 918P and the input of the inverter 919P. Further, the input of the delay circuit 910 is connected to the Q of the flip-flop SR-FFb (provided in the i-th shift register circuit SRb), and the output of the delay circuit 910 is connected to the input of the inverter circuit 918s and the input of the inverter 919s. Here, as shown in FIG. 22, at the time where the OUTB of the level shifter LSa becomes active, the pre-charge pulse serving as an output signal of the inverter circuit 918P becomes active with a delay (this delay is caused by the delay circuit 906). At the time where the OUTB of the level shifter LSa becomes inactive, the pre-charge pulse becomes inactive with a delay (the delay is caused by the delay circuit 906). A conventional art related to the present invention can be found in the following Patent Document 1, for example.    [Patent Document 1] Japanese Unexamined Patent Publication Tokukaihei 7-295520 (published on Nov. 10, 1995)